Investor Relations

• Specification, include function requirement and performance requirement, die area and power estimation
• Solution design, include algorithm design, hardware solution, block diagram and function module.​
• IP RTL coding , mixed signal SOC integration and verification,  FPGA verification​
• Code quality check, simulation (RTL level, pre-layout, post-layout simulation)
• Logic Synthesis  to netlist, PPA optimize
• Timing closure, constrains check
• Formal check

Mass Production Service

• Production planning & control
• Capacity and delivery management
• Logistics management
• Customer demand fulfillment & on time delivery

Product Engineering Service

• MP/Shuttle T/O service
• Production flow setup
• Product reliability qualification
• EFA/PFA diagnosis service
• MP excursion control
• MP yield optimization

Quality Engineering Service

• CFR/RMA field problem solving
• MRB (Material Review Board) management
• SCAR (Supplier Corrective Action Request) management
• Supplier audit program

Test Engineering Service

• CP/FT test tooling (probe card/load board) design & sustain
• CP/FT test program development
• MP excursion control

Package Engineering Service

• Pin assignment and PCB pre-layout
• QFP/QFN/BGA package service
• BGA substrate layout design
• KGD RDL layout design
• SiP/SOC bonding simulation
• Thermal simulation

System Design Service

• System EV boards
• Reference design
• Test boards support
  • Load board design
  • Test board (Socket board and AIP test board)
  • EV boards
  • HTOL/ELFR test board
• Electrical and reliability test

DFT Service

• DC/AC Scan Insert
• ATPG Production
• MBIST
• ROM code change

APR & Timing Closure

• Chip Floorplan /Hierarchical partition
• Power Network Check
• Placement & CTS
• Routing & DFM
• MCMM Timing & Leakage Optimization
• Sign-Off Timing ECO

Physical Verification

• ESD / Latch Up check
• DRC/LVS/Antenna  
• DFM rule check
• Dummy Fill

Low Power

• Clock Gating (ICG)
• Vt Swapping power optimization
• Multi-Vdd island
• UPF design

Power Integrity

• Power & physical network analysis
• Static and Dynamic IR/EM Analysis
• Signal EM analysis

Our analog engineers have experience in analog and mixed signal IC design in various technology nodes, working on 180nm Poly-Sion node down to the most advanced, state of the art 22nm HKMG node.

Through the past we gained experience in design of different analog modules used in the variety of applications from Low Power Data Converter to High-Speed SerDes, such as: PLL, Bandgap reference, ADC, LDO, OpAmp, USB PHY etc.

Alitech analog expertise includes:

• Specification writing and feasibility studies​
• Circuit design and simulation​
• Analog and custom digital layout design​
• Advanced analog layout design in 28/22nm​
• Physical verification of the design (DRC, LVS, ERC, DFM)​
• Layout parasitic extraction and post-layout simulation​
• Cell library and IO library Re-K service​

Alitech can provide in-house development using its own infrastructure or working on the clients infrastructure through VDI or similar technology.

• Multi-core SOC structure
• ALi dram based high performance NOC
• Advanced security solution
• Low power solution
• Integrate ALI own IPs or third party IPs
• modularized pin mux integration
• modularized system control and clock control
• ALI multi IP hybrid simulation environment and test bench
• high quality constraint files
• DFT，Mbist， design for FT，CP
• chip level and IP level FPGA platform verification

Digital

Analog

Major IP

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ASIC Turnkey Service

前端設計	實體晶片整合	生產/供應鍊管理	系統整合/軟體
SOC Design Service Digital Design Service Analog Design Service	BE Design Service	Package and System Design Mass Production Service	Software Service

ASIC Design Flow

ASIC Design Applicaion

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